Lenovo 59P5107 Ficha Técnica descarregar pdf (Página 14)

Low Voltage Intel

Xeon

™

Processor at 1.60 GHz, 2.0 GHz and 2.4 GHz

14 Datasheet

2.3.1 V

Decoupling

Regulator solutions need to provide bulk capacitance with a low Effective Series Resistance (ESR)

and the baseboard designer must ensure a low interconnect resistance from the regulator (or VRM

pins) to the 604-pin socket. Bulk decoupling may be provided on the voltage regulation module

(VRM) to meet help meet the large current swing requirements. The remaining decoupling is

provided on the baseboard. The power delivery path must be capable of delivering enough current

while maintaining the required tolerances (defined in Table 7). For further information regarding

power delivery, decoupling, and layout guidelines, refer to the appropriate platform design

guidelines.

2.3.2 System Bus AGTL+ Decoupling

The Intel

Xeon

™

processor integrates signal termination on the die as well as part of the required

high frequency decoupling capacitance on the processor package. However, additional high

frequency capacitance must be added to the baseboard to properly decouple the return currents

from the system bus. Bulk decoupling must also be provided by the baseboard for proper AGTL+

bus operation. Decoupling guidelines are described in the appropriate platform design guidelines.

2.4 System Bus Clock (BCLK[1:0]) and Processor Clocking

BCLK[1:0] directly controls the system bus interface speed as well as the core frequency of the

processor. As in previous generation processors, the processor core frequency is a multiple of the

BCLK[1:0] frequency. The maximum processor bus ratio multiplier may be set during

manufacturing. The default setting may equal the maximum speed for the processor.

The BCLK[1:0] inputs directly control the operating speed of the system bus interface. The

processor core frequency is configured during reset by using values stored internally during

manufacturing. The stored value sets the highest bus fraction at which the particular processor may

operate.

Clock multiplying within the processor is provided by the internal PLL, which requires a constant

frequency BCLK[1:0] input with exceptions for spread spectrum clocking. Processor DC and AC

specifications for the BCLK[1:0] inputs are provided in Table 7 and Table 12, respectively. These

specifications must be met while also meeting signal integrity requirements as outlined in Chapter

3.0. The processor utilizes a differential clock. Details regarding BCLK[1:0] driver specifications

are provided in the CK00 Clock Synthesizer/Driver Design Guidelines. Table 1 contains the

supported bus fraction ratios and their corresponding core frequencies.

Table 2. Front Side Bus-to-Core Frequency Ratio

Front Side Bus-to-Core Frequency

Ratio

Front Side Bus Frequency Core Frequency

1/16 100 MHz 1.60 GHz

1/18 133 MHz 2.40 GHz

1/20 100 MHz 2.0 GHz

1 2 ... 9 10 11 12 13 14 15 16 17 18 19 ... 101 102

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